原标题：ADI ADF7023-J高性能GMSK收发器解决方案

　　ADI 公司的ADF7023-J是非常低功耗高性能高度集成的2FSK/GFSK/MSK/GMSK收发器,工作频率从902MHz到958MHz,支持的数据速率从1kbps到300kbps.发送RF合成器包括VCO和低噪音分数N锁相环(PLL).输出通路频率分辨率400Hz,输出功率从-20dBm 到+13.5dBm可编程,接收器具有极好的线性,在最大和最小增益的IP3指标分别为-12.2dBm和-11.5dBm,IP2为18.5dBm和 27dBm. ADF7023-J主要用在智能表,IEEE 802.15.4g,家庭自动化,过程和建筑物控制, 无线传感器网络(WSN),无线保健设备等.本文介绍了ADF7023-J主要特性,功能方框图, 2FSK/GFSK/MSK/GMSK解调器和AFC架构图, 典型应用电路图和多种输入匹配电路.

　　The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported.

　　The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications.

　　The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity.

　　The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the Image Rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated.

　　The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver. The ADF7023-J operates with a power supply range of 1.8 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter a low power sleep mode in which the configuration settings are retained in the battery backup random access memory (BBRAM).

　　The ADF7023-J features an ultralow power, on-chip, communications processor. The communications processor, which is an 8-bit RISC processor, performs the radio control,packet management, and smart wake mode (SWM) functionality.

　　The communications processor eases the processing burden of the companion processor by integrating the lower layers of a typical communication protocol stack. The communications processor also permits the download and execution of a set of firmware modules that include image rejection (IR) calibration, advanced encryption standard (AES) encryption, and Reed- Solomon coding.

　　The communications processor provides a simple commandbased radio control interface for the host processor. A singlebyte command transitions the radio between states or performs a radio function.

　　The communications processor provides support for generic packet formats. The packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet profiles. In transmit mode, the communications processor can be configured to add preamble, sync word, and CRC to the payload data stored in packet RAM. In receive mode, the communications processor can detect and interrupt the host processor on reception of preamble, sync word, address, and CRC and store the received payload to packet RAM. The ADF7023-J uses an efficient interrupt system comprising MAC level interrupts and PHY level interrupts that can be individually set. The payload data plus the 16-bit CRC can be encoded/ decoded using Manchester or 8b/10b encoding. Alternatively, data whitening and dewhitening can be applied.

　　The SWM allows the ADF7023-J to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. After wake-up, the ADF7023-J is controlled by the communications processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The smart wake mode can wake the host processor on an interrupt condition. These interrupt conditions can be configured to include the reception of valid preamble, sync word, CRC, or address match. Wake-up from sleep mode can also be triggered by the host processor. For systems requiring very accurate wake-up timing, a 32 kHz oscillator can be used to drive the wake-up timer. Alternatively, the internal RC oscillator can be used, which gives lower current consumption in sleep.

　　The ADF7023-J features an AES engine with hardware acceleration that provides 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits.

　　Both electronic code book (ECB) and Cipher Block Chaining Mode 1 (CBC Mode 1) are supported. The AES engine can be used to encrypt/decrypt packet data and can be used as a standalone engine for encryption/decryption by the host processor. The AES engine is enabled on the ADF7023-J by downloading the AES firmware module to program RAM.An on-chip, 8-bit ADC provides readback of an external analog input, the RSSI signal, or an integrated temperature sensor. An integrated battery voltage monitor raises an interrupt flag to the host processor whenever the battery voltage drops below a userdefined Threshold.

　　ADF7023-J主要特性:

　　Ultralow power, high performance transceiver

　　Frequency bands: 902 MHz to 958 MHz

　　Data rates supported: 1 kbps to 300 kbps

　　1.8 V to 3.6 V power supply

　　Single-ended and differential power amplifiers (PAs)

　　Low IF receiver with programmable IF bandwidths

　　100 kHz, 150 kHz, 200 kHz, 300 kHz

　　Receiver sensitivity (BER)

　　−116 dBm at 1.0 kbps, 2FSK, GFSK

　　−107.5 dBm at 38.4 kbps, 2FSK, GFSK

　　−106.5 dBm at 50 kbps, 2FSK, GFSK

　　−105 dBm at 100 kbps, 2FSK, GFSK

　　−104 dBm at 150 kbps, GFSK, GMSK

　　−103 dBm at 200 kbps, GFSK, GMSK

　　−100.5 dBm at 300 kbps, GFSK, GMSK

　　Very low power consumption

　　12.8 mA in PHY_RX mode (maximum front-end gain)

　　11.9 mA in PHY_RX mode (AGC off, ADC off)

　　24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)

　　0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active)

　　1.28 μA in PHY_SLEEP mode (32 kHz XTAL oscillator active)

　　0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1)

　　RF output power of −0 dBm to +13.5 dBm (single-ended PA)

　　RF output power of −0 dBm to +10 dBm (differential PA)

　　Patented fast settling automatic frequency control (AFC)

　　Digital received signal strength indication (RSSI)

　　Integrated PLL loop filter and Tx/Rx switch

　　Fast automatic voltage controlled oscillator (VCO) calibration

　　Automatic synthesizer bandwidth optimization

　　On-chip, low power, custom 8-bit processor

　　Radio control

　　Packet management

　　Smart wake mode

　　SPORT mode support

　　High speed synchronous serial interface to Tx and Rx Data for direct interfacing to processors and DSPs

　　Packet management support

　　Highly flexible for a wide range of packet formats

　　Insertion/detection of preamble/sync word/CRC/address

　　Manchester and 8b/10b data encoding and decoding

　　Data whitening

　　Smart wake mode

　　Current saving low power mode with autonomous receiver wake up, carrier sense, and packet reception

　　Downloadable firmware modules

　　Image rejection calibration, fully automated (patent pending)

　　128-bit AES encryption/decryption with hardware acceleration and key sizes of 128 bits, 192 bits, and 256 bits

　　Reed-Solomon error correction with hardware acceleration 240-byte packet buffer for Tx/Rx data

　　Efficient SPI control interface with block read/write access

　　Integrated battery alarm and temperature sensor

　　Integrated RC and 32.768 kHz crystal oscillator

　　On-chip, 8-bit ADC

　　5 mm × 5 mm, 32-lead, LFCSP package

　　ADF7023-J应用:

　　Smart metering

　　IEEE 802.15.4g

　　Home automation

　　Process and building control

　　Wireless sensor networks (WSNs)

　　Wireless healthcare

　　图1.ADF7023-J功能方框图

　　图2.2FSK/GFSK/MSK/GMSK解调器和AFC架构图

　　图3.ADF7023-J典型应用电路图

　　图4.ADF7023-J分离的单端PA和LNA匹配电路图

　　图5.ADF7023-J组合的单端PA和LNA匹配电路图

　　图6.ADF7023-J组合的差分PA和LNA匹配电路图

　　图7.ADF7023-J发送天线分集匹配拓扑图