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Microchip PIC32MX5XX M2M CDMA蜂窝网络开发平台方案

来源：中电网

2019-04-29

类别：工业控制

拍明

原标题：Microchip PIC32MX5XX M2M CDMA蜂窝网络开发平台方案

　　microchip公司的PIC32MX5XX/6XX/7XX系列产品是采用MIPS M4K处理器内核的32位高性能MCU,提供了开发嵌入式项目所有的低成本工具和免费的软件,并和16位MCU产品在引脚和外设上兼容,能满足你对处理能力,存储器和外设的设计要求,主要用在网络连接,图像,数字音频和通用嵌入式控制.本文介绍了PIC32MX5XX/6XX/7XX系列产品主要特性,框图与MIPS M4K处理器内核框图和主要特性,以及Microchip M2M CDMA开发平台主要元器件,电路图和PCB布局图.

　　Microchip’s 32-bit portfolio with the MIPS® M4K® offers high performance microcontrollers, and all the tools needed to develop your embedded project. With free software, low cost development tools, and pin/peripheral compatibility from 16-bit product lines, PIC32 MCUs shorten time to market and allow your designs to grow. PIC32 gives your application the processing power, memory and peripherals your design needs!

　　PIC32MX5XX/6XX/7XX 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet Operating Conditions

　　• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz

　　Core: 80 MHz/105 DMIPS MIPS32® M4K®

　　• MIPS16e® mode for up to 40% smaller code size

　　• Code-efficient (C and Assembly) architecture

　　• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

　　Clock Management

　　• 0.9% internal oscillator

　　• Programmable PLLs and oscillator clock sources

　　• Fail-Safe Clock Monitor (FSCM)

　　• Independent Watchdog Timer

　　• Fast wake-up and start-up

　　Power Management

　　• Low-power management modes (Sleep and Idle)

　　• Integrated Power-on Reset, Brown-out Reset

　　• 0.5 mA/MHz dynamic current (typical)

　　• 41 μA IPD current (typical)

　　Graphics Features

　　• External graphics interface with up to 34 Parallel Master Port (PMP) pins:

　　- Interface to external graphics controller

　　- Capable of driving LCD directly with DMA and internal or external memory

　　Analog Features

　　• ADC Module:

　　- 10-bit 1 Msps rate with one Sample and Hold (S&H)

　　- 16 analog inputs

　　- Can operate during Sleep mode

　　• Flexible and independent ADC trigger sources

　　• Comparators:

　　- Two dual-input Comparator modules

　　- Programmable references with 32 voltage points

　　Timers/Output Compare/Input Capture

　　• Five General Purpose Timers:

　　- Five 16-bit and up to two 32-bit Timers/Counters

　　• Five Output Compare (OC) modules

　　• Five Input Capture (IC) modules

　　• Real-Time Clock and Calendar (RTCC) module

　　Communication Interfaces

　　• USB 2.0-compliant Full-Speed OTG controller

　　• 10/100 Mbps Ethernet MAC with MII and RMII interface

　　• CAN module:

　　- 2.0B Active with DeviceNet™ addressing support

　　• Six UART modules (20 Mbps):

　　- Supports LIN 1.2 protocols and IrDA® support

　　• Up to four 4-wire SPI modules (25 Mbps)

　　• Up to five I2C modules (up to 1 Mbaud) with SMBus support

　　• Parallel Master Port (PMP)

　　Direct Memory Access (DMA)

　　• Up to eight channels of hardware DMA with automatic data size detection

　　• 32-bit Programmable Cyclic Redundancy Check (CRC)

　　• Six additional channels dedicated to USB, Ethernet and CAN modules

　　Input/Output

　　• 15 mA or 10 mA source/sink for standard VOH/VOL and

　　up to 22 mA for non-standard VOH1

　　• 5V-tolerant pins

　　• Selectable open drain and pull-ups

　　• External interrupts

　　Qualification and Class B Support

　　• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned

　　• Class B Safety Library, IEC 60730

　　Debugger Development Support

　　• In-circuit and in-application programming

　　• 4-wire MIPS® Enhanced JTAG interface

　　• Unlimited program and six complex data breakpoints

　　• IEEE 1149.2-compatible (JTAG) boundary scan

　　图1. PIC32MX5XX/6XX/7XX 框图

　　MIPS32® M4K®处理器内核

　　The MIPS32® M4K® Processor core is the heart of the PIC32MX5XX/6XX/7XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations.

　　MIPS32® M4K®处理器内核主要特性:

　　• 5-stage pipeline

　　• 32-bit address and data paths

　　• MIPS32® Enhanced Architecture (Release 2)

　　- Multiply-accumulate and multiply-subtract instructions

　　- Targeted multiply instruction

　　- Zero/One detect instructions

　　- WAIT instruction

　　- Conditional move instructions (MOVN, MOVZ)

　　- Vectored interrupts

　　- Programmable exception vector base

　　- Atomic interrupt enable/disable

　　- GPR shadow registers to minimize latency for interrupt handlers

　　- Bit field manipulation instructions

　　• MIPS16e® code compression

　　- 16-bit encoding of 32-bit instructions to improve code density

　　- Special PC-relative instructions for efficient loading of addresses and constants

　　- SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines

　　- Improved support for handling 8-bit and 16-bit data types

　　• Simple Fixed Mapping Translation (FMT) mechanism

　　• Simple dual bus interface

　　- Independent 32-bit address and data busses

　　- Transactions can be aborted to improve interrupt latency

　　• Autonomous multiply/divide unit

　　- Maximum issue rate of one 32x16 multiply per clock

　　- Maximum issue rate of one 32x32 multiply every other clock

　　- Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent)

　　• Power control

　　- Minimum frequency: 0 MHz

　　- Low-Power mode (triggered by WAIT instruction)

　　- Extensive use of local gated clocks

　　• EJTAG debug and instruction trace

　　- Support for single stepping

　　- Virtual instruction and data address/value

　　- Breakpoints

　　- PC tracing with trace compression

　　图2. MIPS32® M4K®处理器内核框图

　　Microchip M2M CDMA开发平台包括:

　　On board PIC32MX795F512L microcontroller @ 80 MHz, 512 KB Flash and 128 KB RAM

　　CDMA Cellular module certified on Verizon wireless network

　　GPS for location aware applications

　　10/100 Ethernet connectivity

　　On board MRF24J40 for Zigbee and MiWi connectivity

　　A serial communication interface for simple wired connectivity

　　Micro SD Card support for code, event or image storage

　　On-board 3-axis accelerometer to monitor motion

　　Temperature and light sensors

　　Two (2) Expansion ports for custom sensing or connectivity development

　　FCC Part 15 Certified

　　The Microchip M2M Development Platform for CDMA provides a Verizon Wireless-certified “out-of-the-box” M2M solution, or can be used as an extensible platform for custom applications. The platform provides a variety of sensors and interfaces to allow the designer to tailor the solution for a specific application.

　　The M2M platform RF software and hardware are certified under the Verizon Wireless Open Development Initiative (ODI) certification specifications, and have been approved for use on the Verizon Wireless network. The application software communicates to the network using the Verizon Device Client Framework (DCF). The DCF software implementation is owned by Verizon, and is provided with the platform as a binary module. Documentation for the DCF API is available from the Microchip M2M web site. Refer to “Verizon M2M Developer Program” for more information.

　　Figure 3 provides a hardware block diagram of the Microchip M2M Development Platform for CDMA.

　　The Microchip M2M Development Platform for CDMA (P/N: DM320017) is a development/evaluation tool designed to be used for research and development in a laboratory environment to enable customers to experiment with software to develop their target endproducts.

　　The DM320017 is certified as FCC Part 15 compliant for use as a finished product in the United States and Canada.

　　The DM320017 carries the CE label for compliance with EU Directive 2011/65/EU (RoHS2). It should not be placed into the EU market (e.g., sale, loan, lease, gift, etc.) without confirmation of inapplicability of or alternatively, compliance to, EU EMC Directive 2004/108/EC as supported by the European Commission’s Guide for the EMC Directive 2004/108/EC.