原标题：Actel IGLOO AGL600视频开发方案

　　Actel 公司的IGLOO系列闪存FPGA采用Flash Freeze 技术和130nm技术制造,具有最低的功耗,可重新编程,占位面积小和单片解决方案. 内核工作电压1.2-1.5V, Flash Freeze模式的功耗仅为5uW.该系列具有15K到100万个系统门,多达144kb 真双端口 SRAM和300个用户I/O.适用于相机、智能电话、便携式媒体播放器和条形码读取器等设备。本文介绍了IGLOO系列闪存FPGA主要特性和优势, 四组I/O器件架构图以及IGLOO视频演示板主要特性, 方框图和详细电路图.

　　The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features.

　　The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low power mode that consumes as little as 5 μW while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode.

　　The Low Power Active capability (static idle) allows for ultra-low power consumption (from 12 μW) while the IGLOO device is completely functional in the system. This allows the IGLOO device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.

　　Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, singlechip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

　　These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

　　IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

　　M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low power consumption and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex- M1 is available for free from Actel for use in M1 IGLOO FPGAs.

　　The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support AES decryption.

　　Flash*Freeze Technology

　　The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power.

　　When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained.

　　The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for portable electronics.

　　IGLOO系列FPGA主要特性和优势:

　　Low Power

　　• 1.2 V to 1.5 V Core Voltage Support for Low Power

　　• Supports Single-Voltage System Operation

　　• 5 μW Power Consumption in Flash*Freeze Mode

　　• Low Power Active FPGA Operation

　　• Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content

　　• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

　　High Capacity

　　• 15 k to 1 Million System Gates

　　• Up to 144 kbits of True Dual-Port SRAM

　　• Up to 300 User I/Os

　　Reprogrammable Flash Technology

　　• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

　　• Live-at-Power-Up (LAPU) Level 0 Support

　　• Single-Chip Solution

　　• Retains Programmed Design When Powered Off

　　• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

　　Performance

　　In-System Programming (ISP) and Security

　　• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532–compliant)†

　　• FlashLock® to Secure FPGA Contents

　　High-Performance Routing Hierarchy

　　• Segmented, Hierarchical Routing and Clock Structure

　　Advanced I/O

　　• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

　　• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

　　• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

　　• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and LVCMOS 2.5 V / 5.0 V Input†

　　• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above)

　　• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

　　• Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V

　　• I/O Registers on Input, Output, and Enable Paths

　　• Hot-Swappable and Cold-Sparing I/Os‡

　　• Programmable Output Slew Rate† and Drive Strength

　　• Weak Pull-Up/-Down

　　• IEEE 1149.1 (JTAG) Boundary Scan Test

　　• Pin-Compatible Packages across the IGLOO Family

　　Clock Conditioning Circuit (CCC) and PLL†

　　• Six CCC Blocks, One with an Integrated PLL

　　• Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback

　　• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

　　Embedded Memory

　　• 1 kbit of FlashROM User Nonvolatile Memory

　　• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

　　• True Dual-Port SRAM (except ×18)†

　　ARM Processor Support in IGLOO FPGAs

　　• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available with or without Debug

　　IGLOO 系列器件表:

　　图1.IGLOO四组I/O器件架构图(AGL250, AGL600, AGL400和AGL1000)

　　IGLOO视频演示板

　　IGLOO Video Demo Kit: A Plug-and-Play Demonstration Platform

　　The IGLOO Video Demo Kit consists of an IGLOO video demo board and your choice of an LCD adapter board. You can choose from two plug-and-play display adapter boards mounted with different LCDs, ranging from 5.5" to 7", and resolutions from QVGA (320x240) to SVGA (800x480). You can also build your own customized LCD adapter board. The IGLOO video demo board has an IGLOO device that interfaces with several video/image sources, such as a digital visual interface (DVI) input and a CMOS sensor interface. In addition, off-chip memory is provided for data buffer and storage.

　　IGLOO视频演示板特性和优势:

　　Rapid evaluation and development platform with choice of multiple LCDs

　　Flexibility of demonstrating different IP cores for display applications

　　Ultra-low power IGLOO FPGA with Flash*Freeze technology

　　Low static power and quick entry/exit from Flash*Freeze mode

　　Free evaluation of IP cores with customizable display functions

　　On-board devices

　　Ultra-low power IGLOO AGL600-FG256 FPGA device

　　Micron 2 MB x 32 SDRAM for frame buffer

　　Numonyx™ 64 MB flash for image and data storage

　　USB microcontroller

　　Interfaces

　　5 user buttons and reset

　　2 RJ-45 connectors for 8 pairs of low-voltage differential signaling (LVDS) outputs

　　Plug-and-play to display adapter board via 50-pin connector

　　DVI-D input

　　26-bit connector for Micron CMOS sensor head board

　　JTAG programming connector

　　图2.IGLOO视频演示板方框图

　　图3.IGLOO视频演示板LCD控制器框图

　　图4.IGLOO视频演示板外形图