原标题：Altera Stratix V DSP开发方案

　　Altera公司的Stratix V FPGA是采用28nm技术,在高端应用中实现了业界最大带宽和最高系统集成度，非常灵活，降低了成本和总功耗。Stratix V FPGA 的优点包括高功效收发器突破了带宽,单芯片提高集成度，降低了成本,提高设计灵活性以及降低系统功耗.主要应用在100-Gb光传送网(OTN)复用转发器,100G以太网(GbE)线路,交叉矩阵和背板交换架构,军事雷达,RF卡和通道卡以及演播视频服务器.

　　Stratix V FPGAs are based on the high-perfo rmance architecture of Stratix IV FPGAs and deliver key architectural innovations to enable designers to achieve higher bandwidth and lower power through an unprecedented level of system integration and ultimate flexibility. These innovations include the in troduction of the Embedded HardCopy®Blocks, 28G transceivers, and partial reconfiguration. Stratix V FPGAs continue to leverage the highly successful Programmable Power Technology used in Stratix III and Stratix IV FPGAs.

　　Lower power consumption and higher bandwidth are now the two dominant requirements in designing next-generation high-end applications. The global trend across multiple markets is for higher bandwidth in the same footprint at the same or lower power and cost. The Internet is goin g mobile and video is driving bandwidth requirements at a growth rate of 50% year on year. The march to 40G and 100G systems (with 400G on the horizon) is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. The next generation of 28-nm high-end Altera®FPGAs addresses these challenges through leading-edge technological innovation, integration, and reduced power consumption.

　　Designing next-generation FPGAs to address the current trend of higher bandwidth and lower power is becoming much more challenging. Many factors must be carefully considered when planning a new FPGA family to ensure the new devices can address the power and performance requirements of the targeted applications in various market segments. These factors include selecting the right process technology, designing the right architecture, applying the right software power optimization, and enabling easier and power-efficient system-level design.

　　Altera took a holistic approach in designing Stratix®V FPGAs to deliver the lowest power and highest bandwidth FPGAs in the industry. Key innovations were introduced at various levels to optimize the Stratix V FPGAs’ power and performance for designers looking to build a higher bandwidth design while reducing thermal power consumption In addition, Altera leveraged the lower voltage offered by the 28HP process to significantly reduce power without impacting performance.

　　The static power and dynamic power savings achieved by Stratix V FPGAs on a 0.85-V supply (on most devices) compared to a 1.0-V supply. Static power is proportional to Vcc3, and by reducing voltage from 1.0 V to 0.85 V, the static power is reduced by 39%. On the other hand, dynamic power is proportional to Vcc2, and a voltage reduction from V to 0.85 V leads to a 28% power reduction.

　　Stratix V FPGAs主要特性:

　　Altera is addressing the requirements of next-generation applications pushing the limit for higher bandwidth and lower power by introducing key innovations on 28-nm Stratix V FPGAs, including:

　　■ 28HP process innovations

　　■ Programmable Power Technology

　　■ Lower voltage (0.85-V) architecture

　　■ High-bandwidth, power-efficient transceivers

　　■ Embedded HardCopy Blocks and extensive hardening of IP

　　■ Hard powering down of functional blocks

　　■ I/O innovations enabling power-efficient memory interfaces

　　■ Quartus II software power optimization

　　■ Logic and RAM clock gating

　　■ Fewer power regulators, switching regulators on all supplies

　　■ Board-level integration: oscillators, decoupling capacitors, OCT

　　■ Easy-to use partial reconfiguration

　　Altera’s comprehensive approach rewards Stratix V customers with many benefits including higher performance and lower power FPGA, higher integration through extensive hardening of IP, and ultimate flexibility through easy-to-use partial reconfiguration. Stratix V FPGAs are the ideal

　　图1. Stratix V FPGAs硬IP框图

　　Stratix® V版DSP开发套件

　　Stratix® V版DSP开发套件提供了全面的设计环境，包括您立即开始开发具有大量DSP功能FPGA设计所需要的全部硬件和软件。开发套件符合RoHS要求。采用这一开发套件，您能够：

　　使用PCIe短卡外形封装兼容开发板，开发并测试PCI Express® (PCIe®)设计，其数据速率高达Gen3(1)。

　　开发并测试含有DDR3或者QDR II存储器的存储器子系统。

　　使用高速中间链接卡(HSMC)连接器来连接Altera合作伙伴(2)提供的35个不同的HSMC，支持Serial RapidIO®、10-Gbps以太网、SONET、CPRI、OBSAI等其他协议。

　　图2. Stratix V GS FPGA开发板外形图

　　Stratix V GX版DSP开发套件包括：

　　Stratix V GS FPGA开发板(参见图1)

　　安装的器件：

　　Stratix V GS FPGA：5SGSMD5K2F40C2N

　　配置、状态和设置单元

　　JTAG

　　板上USB-BlasterTM II电缆

　　通过MAX® V器件和闪存进行快速被动并行(FPP)配置

　　一个复位配置按键

　　一个CPU复位按键

　　两个配置按键

　　时钟

　　50-MHz和125-MHz可编程振荡器

　　SMA输入(LVPECL)

　　通用用户输入和输出

　　10/100/1000Mbps以太网PHY (SGMII)，提供RJ-45 (铜)连接器。

　　16x2字符LCD

　　一个8位置双列直插封装(DIP)开关

　　16个用户LED

　　三个用户按键

　　存储器件

　　DDR3 SDRAM (1,152 MB，x72位宽)

　　QDR II+ SRAM (4.5 MB，2-Mb x18位宽)

　　与QDR II 4-Mb x18位宽引脚布局兼容

　　RLDRAM II (72-Mbyte CIO RLDRAM II，具有18位数据总线)

　　元件和接口

　　PCIe x8边缘连接器

　　两个HSMC连接器

　　串行数字接口(SDI)输入和输出的SMB

　　QSFP光封装

　　10/100/1000Mbps以太网PHY (SGMII)，提供RJ-45 (铜)连接器。

　　电源

　　笔记本计算机直流输入

　　PCIe边缘连接器

　　Nios® II处理器网络服务器，支持系统远程更新。

　　回环和调试HSMC卡

　　电源适配器和电缆

　　Stratix V GS FPGA开发套件软件组成

　　完整的文档

　　用户指南

　　参考手册

　　电路板原理图和布板设计文件

　　基于GUI的电路板测试系统

　　包括完整的Quartus II工程，支持开放源代码RTL。

　　电路板更新入口

　　包括完整的Quartus II工程，支持开放源代码RTL。

　　Quartus II设计软件，开发套件版(DKE)

　　一年内使用完整版Quartus II软件的许可

　　图3. Stratix V GS FPGA开发板主要元件分布图

　　图4. Stratix V GS FPGA开发板框图