原标题：ADI AD9652 310MSPS取样16位ADC评估方案

　　ADI公司的ad9652是双路16位模数转换器(ADC),取样速率高达310MSPS,输入频率高达450MHz是有极好的动态范围,噪音−157.6 dBFS, SFDR超过85dBFS,通路隔离90dB,工作电压3.3V和1.8V,总功耗2.16W,主要用在军用雷达和通信,多模式数字接收器(3G或4G), 测试测量和智能天线系统.本文介绍了AD9652产品亮点和主要特性,功能框图,以及AD9652评估板主要特性,电路图和材料清单.

　　The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.

　　The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.

　　The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

　　The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40℃ to +85℃. This product is protected by pending U.S. patents.

　　AD9652产品亮点:

　　1. Integrated dual, 16-bit, 310 MSPS ADCs.

　　2. On-chip buffer simplifies ADC driver interface.

　　3. Operation from 3.3 V and 1.8 V supplies and a separate digital output driver supply accommodating LVDS outputs.

　　4. Proprietary differential input maintains excellent signal-to-noise ratio (SNR) performance for input frequencies of up to 485 MHz.

　　5. SYNC input allows synchronization of multiple devices.

　　6. Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback.

　　AD9652主要特性:

　　High dynamic range

　　SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)

　　SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)

　　Noise spectral density (NSD) = −156.7 dBFS/Hz input noise at −1 dBFS at 70 MHz

　　NSD = −157.6 dBFS/Hz for small signal at −7dBFS at 70 MHz

　　90 dB channel isolation/crosstalk

　　On-chip dithering (improves small signal linearity)

　　Excellent IF sampling performance

　　SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)

　　SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)

　　Full power bandwidth of 465 MHz

　　On-chip 3.3 V buffer

　　Programmable input span of 2 V p-p to 2.5 V p-p (default)

　　Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)

　　Internal ADC clock duty cycle stabilizer

　　SYNC input allows multichip synchronization

　　Total power consumption: 2.16 W

　　3.3 V and 1.8 V supply voltages

　　DDR LVDS (ANSI-644 levels) outputs

　　Serial port control

　　Energy saving power-down modes

　　AD9652应用:

　　Military radar and communications

　　Multimode digital receivers (3G or 4G)

　　Test and instrumentation

　　Smart antenna systems

　　图1. AD9652功能框图

　　AD9652评估板

　　This user guide describes the AD9652 evaluation board, AD9652-310EBZ, which provides all of the support circuitry required to operate this part in its various modes and configurations. The application software used to interface with the devices is also described.

　　AD9652评估板主要特性:

　　Full featured evaluation board for the AD9652

　　SPI interface for setup and control

　　Balun/transformer or amplifier input drive option

　　On-board LDO regulator needing a single external 6 V, 2 A dc supply

　　VisualAnalog® and SPI controller software interfaces

　　图2. AD9652评估板和HSC-ADC-EVALCZ数据采集板外形图