原标题：ADI AD9680双路14位1GSPS模数转换方案

　　ADI公司的AD9680是双路14位1GSPS模数转换器(ADC),IF取样频率高达2GHz, JESD204B (Subclass 1)码串行数字输出,1GSPS时每路总功耗1.65W,340MHz时的SFDR=dBFS,1GHz时为80dBFS,1GSPS时的噪音密度=-154dBFS/Hz, DNL = ±0.5 LSB INL = ±2.5 LSB, 1.25 V, 2.5 V和3.3 V工作电压,主要用在通信,多频带多模式数字接收器如3G/4G, TD-SCDMA, W-CDMA, GSM, LTE,通用软件无线电,超宽带卫星接收器,仪表,雷达,HFC数字反向通路接收器等.本文介绍了AD9680产品亮点和主要特性,框图, 评估板AD9680-1000EBZ主要特性,测试连接图,电路图,材料清单和PCB设计文件.

　　The AD9680 is a dual, 14-bit, 1 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

　　The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

　　The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters.

　　In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

　　Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.

　　The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.

　　The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40℃ to +85℃ industrial temperature range. This product is protected by a U.S. patent.

　　AD9680产品亮点:

　　1. Wide full power bandwidth supports IF sampling of signals up to 2 GHz.

　　2. Buffered inputs with programmable input termination eases filter design and implementation.

　　3. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.

　　4. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.

　　5. Programmable fast overrange detection.

　　6. 9 mm × 9 mm 64-lead LFCSP

　　AD9680主要特性:

　　JESD204B (Subclass 1) coded serial digital outputs

　　1.65 W total power per channel at 1 GSPS (default settings)

　　SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz

　　SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 61.4 dBFS at 1 GHz

　　ENOB = 10.8 bits at 10 MHz

　　DNL = ±0.5 LSB INL = ±2.5 LSB

　　Noise density = −154 dBFS/Hz at 1 GSPS

　　1.25 V, 2.5 V, and 3.3 V dc supply operation

　　No missing codes

　　Internal ADC voltage reference

　　Flexible input range and termination impedance

　　1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)

　　400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

　　2 GHz usable analog input full power bandwidth

　　95 dB channel isolation/crosstalk

　　Amplitude detect bits for efficient AGC implementation

　　2 integrated wideband digital processors per channel

　　12-bit NCO, up to 4 cascaded half-band filters

　　Differential clock input

　　Integer clock divide by −1, 2, 4, or 8

　　Flexible JESD204B lane configurations

　　Small signal dither

　　AD9680应用:

　　Communications

　　Diversity multiband, multimode digital receivers

　　3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

　　General-purpose software radios

　　Ultrawideband satellite receivers

　　Instrumentation

　　Radars

　　Signals intelligence (SIGINT)

　　DOCSIS 3.0 CMTS upstream receive paths

　　HFC digital reverse path receivers

　　图1. AD9680功能框图

　　AD9680评估板AD9680-1000EBZ

　　This user guide describes the AD9680 evaluation board AD9680-1000EBZ which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described.

　　The AD9680-1000EBZ and AD9234-1000EBZ are evaluation boards for the AD9680-1000 14-Bit, 1000MSPS JESD204B, Dual Analog-to-Digital Converter and the AD9234-1000 12-Bit, 1000MSPS JESD204B, Dual Analog-to-Digital Converter respectively. The reference designs provide all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V1EBZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9680 and AD9234. The user guide wiki provides documentation and instructions to configure the device for performance evaluation in the lab.

　　AD9680评估板AD9680-1000EBZ主要特性:

　　Full featured evaluation board for the AD9680 and AD9234

　　SPI interface for setup and control

　　Wide band Balun driven input

　　No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC

　　VisualAnalog® and SPI controller software interfaces

　　图2. 评估板AD9680-1000EBZ外形图

　　图3. 评估板AD9680-1000EBZ测试连接图