原标题：POL电源设计技术和参考设计

　　由于更高的集成度、更快的处理器运行速度以及更小的特征尺寸，内核及I/O电压的负载点(POL)处理器电源设计变得越来越具挑战性。处理器技术的发展必须和POL电源设计技术相匹配。5年或10年以前使用的电源管理解决方案，对于当今的高性能处理器而言，可能不再那么行之有效了。因此，当我们为TI的DaVinci数字信号处理器 (DSP)进行POL电源解决方案设计时，对基本电源技术的充分了解可以帮助我们克服许多设计困难。本文将对一系列适用于该DaVinci处理器的电源去耦、浪涌电流、稳压精度和排序技术进行讨论。我们将以使用了 TI 电源管理产品的一个电源管理参考设计为例来提供对这些论述的支持。

　　能量之源——大型旁路去耦电容

　　处理器所使用的全部电流除了由电源本身提供以外，处理器旁路和一些电源的大型电容也是提供电流的重要来源。当处理器的任务级别(level of activity)急剧变化而出现陡峭的负载瞬态时，首先由一些本地旁路电容提供瞬时电流——这种电容通常为小型陶瓷电容，其可以对负载的变化快速响应。随着处理速度的增加，对于更多能量存储旁路电容的需求变得更为重要。另一个能量来源是电源的大型电容。为了避免出现稳定性问题，必须注意一定要确保电源的稳定性，并且可以利用添加的旁路电容正确地启动。因此，我们要保证对电源反馈回路的补偿以适应额外的旁路电容。电源评估板 (EVM) 在试验台上可能非常有效，但在负载附近添加了许多旁路电容的情况下其性能可能会发生变化。

　　作为一个经验法则，我们可以通过尽可能近的在处理器功率引脚处放置多个0603或0402电容(60用于内核电压，而30用于DM6443的I/O电压)，从而将DaVinci电源电压从系统噪声中完全去耦。更小型的0402电容是较好的选择，因为其寄生电感较低。较小的电容值(例如，560pF)应该最为接近功率引脚，其距离仅为1.25cm。其次，最为接近功率引脚的是中型旁路电容(例如，220nF)。建议每个电源至少要使用8个小型电容和8个中型电容，并且应紧挨着BGA过孔安装(占用内部BGA空间，或者至少应在外部角落处)。在更远一点的地方，可以安装一些较大的大型电容，但也应该尽可能地靠近处理器。

　　浪涌电流

　　具有大旁路电容的电源存在启动问题，因为电源可能无法对旁路电容充电，而其正是启动期间满足处理器要求所需要的。因此，在启动期间，过电流可能会引起电源的关断，或者电压可能会暂时地下降(变为非单调状态)。一个很好的设计实践是确保电压在启动期间不发生压降、过冲或承受长时间的高压状态。为了减少浪涌电流，可以通过增加内核电压电源的启动时间，来允许旁路电容缓慢地充电。许多DC/DC调节器都具有独特的可调软启动引脚，以延长电压斜坡时间。如果调节器不具有这种软启动引脚，那么我们可以利用一个外部 MOSFET 以及一种RC充电方案，来从外部对其进行实施。我们还推荐使用一种带有电流限制功能的DC/DC调节器，来帮助维持一种单调的电压斜坡。实施一个软启动方案有助于满足DaVinci处理器的排序要求。

　　排序

　　越来越多的处理器厂商将提供推荐的内核及I/O上电排序的时序准则。一旦获知时序要求，POL电源设计人员便可选择一种适当的技术。对一个双路电源上电和断电的方法有很多种：顺序排序和同时排序是最为常用的两种方法。

　　当在内核和I/O上电之间要求一个较短的毫秒级时间间隔时，我们就可以实施顺序排序。实施顺序排序的一种方法是，只需将一个稳压器的 PWERGOOD引脚连接至另一个稳压器的ENABLE引脚即可。当内核和I/O电压差在上电和断电期间需要被最小化时，就需要使用同时排序。要实施同时排序，内核和I/O电压应彼此紧密地跟踪，直到达到较低的理想电压电平。在这一点上，较低的内核电压达到了其设定值要求，而较高的I/O电压将可以继续上升至其设定值。

　　在自升压模式中，DaVinci处理器要求对CVDD和CVDDDSP内核电源进行同时排序。在主机升压模式中，CVDD 必须斜坡上升，并在CVDDSP开始斜坡上升以前达到其设置值(1.2V)。作为一个最大值，CVDDDSP 电源必须在关闭(开启)“始终开启”和DSP域之间的短路开关以前上电。我们可以以任何顺序启动I/O电源(DVDD18、DVDDR2和DVDD33)，但是必须在CVDD电源100ms的同时达到其设定值。

　　稳压精度

　　电源系统的电压容差有几个影响因素。电压基准精度就是最为重要的一个影响因素，我们可以在电源管理器件的产品说明书中找到其规范。新型稳压器要求达到±1%的精度或更高的温度基准精度。一些成本较低的稳压器可能会要求±2%或±3%的基准电压精度。请在产品说明书中查看稳压器厂商的相关规范，以确保稳压精度可以满足处理器的要求。另一个影响稳压精度的因素是稳压器外部反馈电阻的容差。

　　在要求精确容差值的情况下，我们推荐使用±1%的容差电阻。另外，在将这种电阻用于编程输出电压时，其将会提供额外±0.5%的精度。具体的计算公式如下：

　　输出电压精度=2×(1-VREF/VOUT)×TOLRES

　　第三个影响因素是输出纹波电压。一个卓越的设计实践是针对低于1%输出电压的峰至峰输出电压进行设计，其可使电源系统的电压精度提高±0.5%。假设为±2%基准精度，那么这3个影响因素加在一起则为±3%的电源系统精度。

　　DaVinci CVDD电源要求一个可带来±4.2%精度的50mV容差的1.2V典型内核电源。3.3V DVDD电源具有一个可带来±4.5%精度的150mV的容差，而1.8V DVDD电源则具有一个可带来±5%精度的90mV的容差。使稳压器靠近负载来减少路由损耗是非常重要的。需要注意的是，如果电源具有3%的容差，且处理器内核电压要求具有4.2%容差的情况下，我们就必须对去耦网络进行设计，以能够适应1.2V电压轨的1.2%精度或14mV容差。

　　历史经验数据显示，内核电压随着处理技术的发展而不断降低。对内核电压稍作改变，便可提供更高的性能，或节省更多的电量。选择一个具有可编程输出电压和±3% 以上输出电压容差的稳压器是一种较好的设计方法。相比从零开始重新设计一种全新的电源，简单的电阻器变化或引脚重新配置要容易得多。因此，我们要选择一款可以支持低至0.9V或更低输出电压的稳压器，以能够最大化地重用，并帮助简化TI片上系统(SoC)器件未来版本的使用。

　　参考设计

　　我们构建了若干电源管理参考设计，并经过数字音频/视频应用的测试。这些应用均使用了TI的TMS320DM6443和TMS320DM6446处理器，其能够满足排序、电压精度和启动要求。图1显示了12V电源的参考设计，该设计使用了TPS62111同步降压转换器、TPS62040同步降压转换器以及TPS73618低压降调节器，以分别提供3.3V、1.2V和1.8V电压轨。这种参考设计包含了一个简单的外部MOSFET、电阻和电容延迟电路，以使3.3V电压轨能够适应自升压模式排序方案要求。TPS62040不但提供了1.2V的内核电压，而且还可满足引脚5软启动电容的排序要求。这种解决方案拥有±3%容差，90%以上的效率。为了能够适应主机升压模式排序方案要求，我们可以添加一个类似的MOSFET、电阻以及电容电路添加至1.2V电压轨。

　　图1显示了复位电路，该电路使用TPS3808和TPS3803电源电压监控器来监控电压轨的变化情况。请您使用最小值的TPS3808G01(U5)，来安装图中所示的复位电路电源。如果需要超过3.3V电压轨的1.5A电流和1.2V电压轨的1.2A电流的话，那么TPS54350和TPS54110 SWIFTTM DC/DC转换器可能会被分别用于实现3A和1.5A电流。SWIFT稳压器具有基于DaVinci技术的数字视频EVM的特点。

　　图1 轨电压复位和电压监控电路

　　总结

　　一旦充分了解了去耦、排序和容差要求以后，为DaVinci处理器设计一款电源解决方案就变得非常简单明了。在为所有高性能处理器设计电源时，坚持使用上述技术是一个相当不错的设计实践。

　　描述

　　【TMS320DM6443】

　　The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

　　The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

　　The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

　　The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

　　The ARM core incorporates:

　　A coprocessor 15 (CP15) and protection module

　　Data and program Memory Management Units (MMUs) with table look-aside buffers.

　　Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

　　The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

　　Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

　　With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

　　The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

　　The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

　　The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

　　The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

　　The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

　　The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

　　The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

　　The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

　　The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

　　The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

　　特性

　　Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!

　　High-Performance Digital Media SoC

　　594-MHz C64x+™ Clock Rate

　　297-MHz ARM926EJ-S™ Clock Rate

　　Eight 32-Bit C64x+ Instructions/Cycle

　　4752 C64x+ MIPS

　　Fully Software-Compatible With C64x /ARM9™

　　Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core

　　Eight Highly Independent Functional Units

　　Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

　　Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle

　　Load-Store Architecture With Non-Aligned Support

　　64 32-Bit General-Purpose Registers

　　Instruction Packing Reduces Code Size

　　All Instructions Conditional

　　Additional C64x+™ Enhancements

　　Protected Mode Operation

　　Exceptions Support for Error Detection and Program Redirection

　　Hardware Support for Modulo Loop Operation

　　C64x+ Instruction Set Features

　　Byte-Addressable (8-/16-/32-/64-Bit Data)

　　8-Bit Overflow Protection

　　Bit-Field Extract, Set, Clear

　　Normalization, Saturation, Bit-Counting

　　Compact 16-Bit Instructions

　　Additional Instructions to Support Complex Multiplies

　　C64x+ L1/L2 Memory Architecture

　　32K-Byte L1P Program RAM/Cache (Direct Mapped)

　　80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)

　　64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)

　　ARM926EJ-S (MPU) Core

　　Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets

　　DSP Instruction Extensions and Single Cycle MAC

　　ARM® Jazelle® Technology

　　EmbeddedICE-RT™ Logic for Real-Time Debug

　　ARM9 Memory Architecture

　　16K-Byte Instruction Cache

　　8K-Byte Data Cache

　　16K-Byte RAM

　　16K-Byte ROM

　　Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug

　　Endianness: Little Endian for ARM and DSP

　　Video Processing Subsystem

　　Resize Engine Provides:

　　Resize Images From 1/4x to 4x

　　Separate Horizontal and Vertical Control

　　Back End Provides:

　　Hardware On-Screen Display (OSD)

　　4 - 54 MHz DACs for a Combination of

　　Composite NTSC/PAL Video

　　Luma/Chroma Separate Video (S-video)

　　Component (YPbPr or RGB) Video (Progressive)

　　Digital Output

　　8-/16-Bit YUV or up to 24-Bit RGB

　　HD Resolution

　　Up to 2 Video Windows

　　External Memory Interfaces (EMIFs)

　　32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)

　　Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach

　　Flash Memory Interfaces

　　NOR (8-/16-Bit-Wide Data)

　　NAND (8-/16-Bit-Wide Data)

　　Flash Card Interfaces

　　Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)

　　CompactFlash Controller With True IDE Mode

　　SmartMedia

　　Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)

　　Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)

　　One 64-Bit Watch Dog Timer

　　Three UARTs (One with RTS and CTS Flow Control)

　　One Serial Port Interface (SPI) with Two Chip-Selects

　　Master/Slave Inter-Integrated Circuit (I2C Bus™)

　　Audio Serial Port (ASP)

　　I2S

　　AC97 Audio Codec Interface

　　Standard Voice Codec Interface (AIC12)

　　10/100 Mb/s Ethernet MAC (EMAC)

　　IEEE 802.3 Compliant

　　Media Independent Interface (MII)

　　VLYNQ™ Interface (FPGA Interface)

　　Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data

　　USB Port With Integrated 2.0 PHY

　　USB 2.0 High-/Full-Speed (480 Mbps) Client

　　USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)

　　Three Pulse Width Modulator (PWM) Outputs

　　On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART

　　ATA/ATAPI I/F (ATA/ATAPI-6 Specification)

　　Individual Power-Saving Modes for ARM/DSP

　　Flexible PLL Clock Generators

　　IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

　　Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)

　　361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch

　　0.09-µm/6-Level Cu Metal Process (CMOS)

　　3.3-V and 1.8-V I/O, 1.2-V Internal

　　Applications:

　　Digital Media

　　Networked Media Encode/Decode

　　Video Imaging

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