原标题：Fast controller IP harnesses HBM3 memory

　　Comprising fully integrated PHY and digital controller IP, the Rambus HBM3-ready memory interface subsystem operates at up to 8.4 Gbps. This data rate is more than double that of the Rambus HBM2E memory subsystem and enables terabyte-scale–bandwidth accelerators for artificial intelligence, machine learning, and high-performance computing applications.

　　High-Bandwidth Memory Generation 3, or HBM3, is faster, consumes less power, and supports higher capacity compared to HBM2 memory. The Rambus HBM3 memory interface subsystem provides 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this achieves a total interface bandwidth of 1075.2 GB/s per stack, with the stack consisting of 2, 4, 8, 12, or 16 HBM3 DRAM devices.

　　Look-ahead command processing maximizes memory bandwidth and minimizes latency. A DFI-compatible interface eases controller/PHY integration, and either the memory controller or PHY can be an ASIC interface master (PHY independent mode). The subsystem also supports HBM3 reliability, availability, and serviceability (RAS) features, such as error correcting code (ECC), and includes a hardware-level performance activity monitor.

　　A 2.5D package and interposer reference design is included as part of the memory subsystem IP license, while the LabStation development environment enables quick system bring-up, characterization, and debugging. Alternatively, the HBM3 PHY and controller IP cores can be licensed separately to be paired with third-party HBM3 controller or PHY solutions.

　　HBM3 PHY product page

　　HBM3 controller product page

　　Rambus

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