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基于NXP公司的LS1021A时间敏感网络(TSN)参考设计

来源：中电网

2018-10-19

类别：无线互联

310

拍明

原标题：NXP LS1021A时间敏感网络(TSN)参考设计

　　nxp公司的LS1021A是成本效益节能的高度集成系统级芯片(SoC),采用32位ARMCortexR-A7核,以及具有ECC保护L1和L2缓冲存储器,运营频率高达1GHz,CoreMarkR性能高达5000,主要用在网络和无线接入点,工业网关,工业自动化,打印,图像,企业和消费类M2M,网络和路由器以及智能无流.本文介绍了LS1021A主要特性,框图,物联网(IoT)智能连接解决方案以及LS1021A时间敏感网络(TSN)参考设计主要特性和电路图.

　　A member of the Layerscape (LS1) series, the LS102xA family is a cost-effective,

　　power-efficient, and highly integrated system-on-chip (SoC) design that extends the

　　reach of the NXP value-performance line of QorIQ communications processors.

　　Featuring a pair of extremely power-efficient 32-bit ARMR CortexR-A7 cores with

　　ECC-protected L1 and L2 cache memories for high reliability, running up to 1 GHz, and

　　providing pre-silicon CoreMarkR performance of over 5,000, the LS102xA family

　　delivers greater performance than any previous sub-4W communication processor.

　　This chip can be used for networking and wireless access points, industrial gateways,

　　industrial automation, printing, imaging, and M2M for enterprise and consumer

　　networking and router applications.

　　The QorIQ LS1 family, which includes the LS1021A communications processor, is built on Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale..

　　A member of the value-performance tier, the QorIQ LS1021A processor provides extensive integration and power efficiency for fanless, small form factor enterprise networking applications. Incorporating dual ARM® Cortex®-A7 cores running up to 1.2 GHz, the LS1021A processor is engineered to deliver CoreMark® performance of over 7,000, as well as virtualization support, advanced security features and the broadest array of high-speed interconnects and optimized peripheral features ever offered in a sub-3 W processor.

　　The QorIQ LS1021A processor features an integrated LCD controller, CAN controller for implementing industrial protocols, DDR3L/4 running up to 1600 MHz, integrated security engine and QUICC Engine, and ECC protection on both L1 and L2 caches. The LS1021A processor is pin- and software-compatible with the QorIQ LS1020A and LS1022A processors.

　　LS1021A主要特性:

　　• ARMR CortexR-A7 MPCore compliant with ARMv7-A™ architecture

　　• LS1021A contains a dual-core Cortex-A7. Each coreincludes:

　　– 32 KB L1 Instruction Cache (ECC protection)

　　– 32 KB L1 Data Cache (ECC protection)

　　– NEON co-processor

　　– Floating Point (FPU)

　　– QorIQ Trust Architecture and ARM TrustZoneR

　　• Snoop Control Unit (SCU)

　　• 512 KB unified I/D L2 Cache (ECC protection)

　　• Hierarchical interconnect fabric

　　– The platform has a single 128-bit AMBA 4 AXICoherency Extensions (ACE) master port, whichconnects to CCI-400 Interconnect.

　　• One 8/16/32-bit DDR3L/DDR4 SDRAM memorycontrollers

　　– ECC and interleaving support

　　• VeTSEC Ethernet complex

　　– Up to 3x Gigabit Ethernet

　　– MII, RMII, RGMII, and SGMII support

　　– QoS, lossless flow control, and IEEER 1588

　　• Up to 4 SerDes lanes for high-speed peripheralinterfaces

　　– Two PCI Express Gen2 controllers

　　– One Serial ATA 3.0 (SATA 1.5, 3.0, 6.0 Gbps)controller

　　– Two SGMII interfaces supporting 1000 Mbps

　　• Integrated audio block

　　– Four synchronous audio interfaces (SAI)

　　– I2S, AC97, and Codec/DSP interfaces

　　– Sony/Philips Digital Interconnect Format (S/PDIF)

　　– Asynchronous Sample Rate Converter (ASRC)

　　• Additional peripheral interfaces

　　– One high-speed USB 3.0 controller with integratedPHY

　　– One high-speed USB 2.0 controller with ULPI

　　– Enhanced secure digital host controller(eSDHC/MMC/eMMC)

　　– Three I2C controllers

　　– Four FlexCAN modules

　　– FlexTimer/PWM

　　– SPI interface

　　– QuadSPI controller

　　– Two DUARTs

　　– Six LPUART interfaces

　　– Integrated flash controller supporting NAND andNOR flash

　　– Display controller unit (2D-ACE) 24-bit RGB (12-bit DDR pin interface)

　　– TDM interface

　　– Four GPIO controllers supporting up to 109 generalpurpose I/O signals

　　– One 4-channel qDMA controller and one eDMAcontroller

　　– Global programmable interrupt controller (GIC)

　　– Thermal monitoring unit (TMU)

　　• QUICC Engine ULite block

　　– 32-bit RISC controller for flexible support of thecommunications peripherals

　　– Serial DMA channel for receive and transmit on allserial channels

　　– Two universal communication controllers (TDMand HDLC) supporting 64 multichannels, eachrunning at 64 Kbps

　　• 525 FC-PBGA package, 19 mm x 19 mm

　　LS1021A应用:

　　Industrial

　　Smart homes and buildings

　　Smart cities, smart grid

　　M2M, Industry 4.0

　　Intelligent logistics

　　Consumer

　　Mobile audio

　　High-speed Interfaces

　　Gaming

　　Personal health and fitness

　　Healthcare

　　图1.LS1021A框图

　　物联网(IoT)智能连接解决方案

　　图2.物联网(IoT)智能连接解决方案示意图

　　LS1021A时间敏感网络(TSN)参考设计

　　The LS1021A Time-Sensitive Networking (TSN) Reference Design is a platform that allows developers to design solutions with the new IEEE Time-Sensitive Networking (TSN) standard. The board includes the QorIQLayerscape LS1021A industrial applications processor and SJA1105T TSN switch. The LS1021ATSN is supported by an industrial Linux SDK with Xenomai real time Linux, which also provides utilities for configuring TSN on the SJA1105T.

　　With virtualization support, trust architecture secure platform, Gigabit Ethernet, SATA interface, and an Arduino Shield connector for multiple wireless modules, the LS1021ATSN is ready to support industrial IoT requirements.