基于RENESAS RZ/T1系列SOC的EtherCAT从站解决方案
概述
EtherCAT 是一种实时工业以太网技术 ,采用标准以太网帧(IEEE 802.3),可通过分布
时钟的精确校准实现精准同步 (<< 1μs!)。EtherCAT 系统配置简单,支持各种拓扑结构,如线型、星型、树型、总线型,同时可实现多层次拓扑,每个EtherCAT 网段可容纳65,535 个节点,网络规模几乎无限。EtherCAT 通信速率为2 x 100 Mbit/s,采用全双工模式实现高速通信。EtherCAT 采用主从式结构,从站需要专用EtherCAT 芯片或具有EtherCAT 硬件IP 的硬件芯片实现,这样可以使整个协议处理过程都在硬件中进行,使网络性能达到最优,保证网络的实时性和高速性。
优势
· RENESAS RZ/T1 系列SOC,内置EtherCAT 从站控制器,支持标准EtherCAT 通信协议,采用ARMCortex-R4F 内核,最高支持600MHz 主频,高速实时响应。
【RZ/T1】
Realize Real-Time Control of Industrial Equipment and Networking at the Same Time
The RZ/T1 Group has the Arm® Cortex®-R4 Processor with FPU core, which was designed for real-time processing, and is capable of high-speed operation at up to 600 MHz. Furthermore, access does not need to be performed via cache memory, and tightly-coupled memory capable of definitive real-time response processing is built-in, enabling high-speed access from the CPU without passing through the cache memory.
RZ/T1 devices that are equipped with a built-in R-IN engine, an accelerator for industrial Ethernet communications, can perform industrial Ethernet processing without loss of real-time performance by Hardware RTOS (HW-RTOS)
RZ/T1 devices that are equipped with a configurable absolute encoder interface are perfectly suited for precision motion control applications. The range of industry standards that are supported by the configurable encoder interface includes EnDat2.2, BiSS®-C, A-format™, Tamagawa and HIPERFACE® DSL.
Key Features : RZ/T1(with R-IN engine)
ITEM | RZ/T1(with R-IN engine) | |||
---|---|---|---|---|
Part NAME | R7S910015 | R7S910016 | R7S910017 | R7S910018 |
Packages | 320FPBGA | |||
0.8mm pitch | ||||
17mm x 17mm | ||||
Main CPU | Arm®Cortex®-R4 Processor with FPU | |||
Maximum operating frequency | 450MHz | 600MHz | ||
FPU | Supports single-precision and double-precision addition, subtraction, multiplication, division, multiply-accumulation, and square root calculation | |||
Tightly-coupled memory | ATCM: 512 KB (with ECC); BTCM: 32 KB (with ECC) | |||
Cache memory | Instruction cache: 8 KB (with ECC); data cache: 8 KB (with ECC) | |||
Communication accelerator | R-IN engine multi-protocol communication accelerator | |||
Expanded internal SRAM | 1 MB (with ECC) *also used for storing protocol stack | |||
Clocks | External clock/resonator input frequency: 25 MHz | |||
CPU clock frequency: up to 450/600 MHz | ||||
Low-speed on-chip oscillator (LOCO): 240 kHz | ||||
Timers | Up to 33 expanded timer functions | |||
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4 channels): input capture, output compare, PWM waveform output | ||||
16-bit CMT (6 channels), 32-bit CMTW (2 channels) | ||||
Communications | EtherMAC: 1 port (with switching) | |||
EtherCAT slave controller | ||||
USB 2.0 high-speed host/function: 1 channel | ||||
CAN (ISO 11898-1 compliant): up to 2 channels | ||||
16-byte SCIFA with FIFO: 5 channels | ||||
I2C bus interface: 2 channels of up to 400 kbps transfer speed | ||||
RSPIa: 4 channels | ||||
SPIBSC: 1 channel of multi-I/O serial flash memory connectable | ||||
Memory interfaces | SPI 4ch | |||
QSPI(Flash I/F) with Direct Access from CPU | ||||
SRAM I/F(32bit bus) | ||||
SDRAM I/F(32bit bus) | ||||
Burst ROM I/F(32bit bus) | ||||
Encoder interfaces | - | A-format™, BiSS®-C, EnDat2.2, HIPERFACE®DSL, Tamagawa | - | A-format™, BiSS®-C, EnDat2.2, HIPERFACE®DSL, Tamagawa |
A/D converter | 12-bit A/D converter: 2 units (unit 0: 8 channels; unit 1: 16 channels) | |||
DMA | 16 channels x 2 units | |||
Other functions | Built-in temperature sensor for measuring internal chip temperature | |||
Safety features (register write protection, input clock oscillation stop detection, CRC, IWDTa, A/D self-diagnostics, error control module, etc.) | ||||
Security functions (option): Secure boot, JTAG lock, etc. | ||||
Power supply voltage | 3.3 V (I/O), 1.2 V (internal) | |||
Operating temperature range | Tj = -40℃ ~ +125℃ |
Pin Count / Memory Size:
SRAM
1568KB | ● | |
---|---|---|
544KB | ● | ● |
Pins | 176 | 320 |
Block Diagram:
with R-IN engine
without R-IN engine
*Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
*EtherCAT is a patented technology that Renesas has licensed from Beckhoff Automation GmbH, and is a registered trademark.
*EtherNet/IP is a trademark of ODVA.
*BiSS is a registered trademark of iC-Haus.
*CAN(Controller Area Network):An automotive network specification developed by Robert Bosch GmbH of Germany.
*All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.
* A-format is a trademark of the Nikon Corporation.
*HIPERFACE DSL is registered trademark of SICK STEGMANN GmbH.
*EnDat is registered trademark of DR. JOHANNES HEIDENHAIN GmbH.
主控器件:
R7S910015
R7S910016
R7S910017
R7S910018
R7S910001
R7S910002
R7S910011
R7S910006
R7S910007
R7S910013
R7S910025
R7S910026
R7S910027
R7S910028
R7S910035
R7S910036
【EtherCAT】
EtherCAT(以太网控制自动化技术)是一个以以太网为基础的开放架构的现场总线系统,EtherCAT名称中的CAT为Control Automation Technology(控制自动化技术)首字母的缩写。最初由德国倍福自动化有限公司(Beckhoff Automation GmbH) 研发。EtherCAT为系统的实时性能和拓扑的灵活性树立了新的标准,同时,它还符合甚至降低了现场总线的使用成本。EtherCAT的特点还包括高精度设备同步,可选线缆冗余,和功能性安全协议(SIL3)。
目前有多种用于提供实时功能的以太网方案:例如,通过较高级的协议层禁止CSMA/CD存取过程,并使用时间片或轮询过程来取代它。其它方案使用专用交换机,并采用精确的时间控制方式分配以太网数据包。尽管这些解决方案能够比较快和比较准确地将数据包传送到所连接的以太网节点,但带宽的利用率却很低,特别是对于典型的自动化设备,因为即使对于非常小的数据量,也必须要发送一个完整的以太网帧。而且,重新定向到输出或驱动控制器,以及读取输入数据所需的时间主要取决于执行方式。通常也需要使用一条子总线,特别是在模块化I/O系统中,这些系统与Beckhoff K-总线一样,通过同步子总线系统加快传输速度,但是这样的同步将无法避免引起通讯总线传输的延迟。
通过采用EtherCAT技术, Beckhoff突破了其它以太网解决方案的这些系统限制:不必再像从前那样在每个连接点接收以太网数据包,然后进行解码并复制为过程数据。当帧通过每一个设备(包括底层端子设备)时,EtherCAT从站控制器读取对于该设备十分重要的数据。同样,输入数据可以在报文通过时插入至报文中。在帧被传递 (仅被延迟几位)过去的时候,从站会识别出相关命令,并进行处理。此过程是在从站控制器中通过硬件实现的,因此与协议堆栈软件的实时运行系统或处理器性能无关。网段中的最后一个EtherCAT从站将经过充分处理的报文返回,这样该报文就作为一个响应报文由第一个从站返回到主站。
从以太网的角度看,EtherCAT总线网段只是一个可接收和发送以太网帧的大型以太网设备。但是,该“设备”不包含带下游微处理器的单个以太网控制器,而只包含大量的EtherCAT从站。与其它任何以太网一样,EtherCAT不需要通过交换机就可以建立通讯,因而产生一个纯粹的EtherCAT系统。
责任编辑:Davia
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