原标题：ADI AD9467 16位250MSPS模数转换解决方案

　　ADI公司的AD9467是16位取样频率200MSPS/250MSPS模数转换器(ADC), 工作电压1.8V和3.3V,低压差分输入时钟, 160 MSPS (@ −1 dBFS)取样100MHz的SFDR为100dBFS,具有极好的线性度: DNL = ±1.0 LSB和INL = ±3.0 LSB,差分输入2V-2.5Vp-p,主要用在多载波多模式蜂窝接收器,天线阵列定位,功率放大器线性化,无线宽带,雷达,红外图像以及通信仪表.本文介绍了AD9467主要特性, 功能方框图, 差分变压器耦合配置图以及AD9467用户评估板电路图和材料清单.

　　AD9467: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter

　　The AD9467 is a 16-bit, monolithic, IF sampling analog-to digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range.

　　The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.

　　A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI and typically consumes less than 5 mW when disabled.

　　Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns.

　　The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range.

　　AD9467产品亮点:

　　1. IF optimization capability used to improve SFDR.

　　2. Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.

　　3. Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.

　　4. Packaged in a Pb-free, 72-lead LFCSP package.

　　5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.

　　6. Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS.

　　AD9467主要特性:

　　75.5 dBFS SNR to 170 MHz at 250 MSPS @ 2.5 V p-p FS

　　74 dBFS SNR to 170 MHz at 250 MSPS @ 2.0 V p-p FS

　　90 dBFS SFDR to 300 MHz at 250 MSPS (@ −1 dBFS) at 2.5 V p-p FS

　　95 dBFS SFDR to 170 MHz at 250 MSPS (@ −1 dBFS) at 2.0 V p-p FS

　　100 dBFS SFDR at 100 MHz at 160 MSPS (@ −1 dBFS)

　　60 fs rms Jitter

　　Excellent linearity

　　DNL = ±1.0 LSB typical

　　INL = ±3.0 LSB typical

　　2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable)

　　Integrated input buffer

　　External reference support option

　　Clock duty cycle stabilizer

　　Output clock available

　　Serial port control

　　Built-in selectable digital test pattern generation

　　Selectable output data format

　　LVDS outputs (ANSI-644 compatible)

　　1.8 V and 3.3 V supply operation

　　AD9467应用:

　　Multicarrier, multimode cellular receivers

　　Antenna array positioning

　　Power amplifier linearization

　　Broadband wireless

　　Radar

　　Infrared imaging

　　Communications instrumentatio

　　图1.AD9467功能方框图

　　图2.AD9467差分变压器耦合配置图:高达150MHz基带应用

　　图3.AD9467差分变压器耦合配置图: 150MHz-300MHz IF应用

　　图3.AD9467采用ADL5562的差分输入配置图

　　AD9467用户评估板

　　图4.AD9467用户评估板电路图(1)

　　图5.AD9467用户评估板电路图(2)

　　图6.AD9467用户评估板电路图(3)

　　图7.AD9467用户评估板电路图(4)

　　图8.AD9467用户评估板电路图(5)

　　图9.AD9467用户评估板电路图(6)

　　图10.AD9467用户评估板电路图(7)

　　AD9467用户评估板电路图材料清单: