NXP PCF85132低速率LCD驱动方案
原标题:NXP PCF85132低速率LCD驱动方案
nxp 公司的PCF85132是低速率LCD驱动器,能产生驱动任何静态或低速LCD(包含四个屏面和160段)的信号,和大多数微出版业器或MCU兼容,采用两线双向I2C总线通信,显示数据存储器器160x4位RAM,电源电压1.8V-5.5V,LCD和逻辑控制电源可单独使用。本文介绍了PCF85132主要特性和优势,方框图,两个PCF85132级联配置图以及一个PCF85132和一个PCF85133级联配置图。
PCF85132:LCD driver for low multiplex rates
The PCF85132 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 160 segments. It can be easily cascaded for larger LCD applications. The PCF85132 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes).
PCF85132主要特性和优势:
Single-chip LCD controller and driver for up to 640 elements
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
160 segment drives:
Up to eighty 7-segment numeric characters
Up to forty 14-segment alphanumeric characters
Any graphics of up to 640 elements
May be cascaded for large LCD applications (up to 5120 elements possible)
160 × 4-bit RAM for display data storage
Software programmable frame frequency in steps of 5 Hz in the range of 60 Hz to 90 Hz; factory calibrated
Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs
Internal LCD bias generation with voltage-follower buffers
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Wide power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption, typical: IDD = 4 μA, IDD(LCD) = 30 μA
400 kHz I2C-bus interface
Auto-incremental display data loading across device subaddress boundaries
Versatile blinking modes
Compatible with Chip-On-Glass (COG) technology
No external components
Two sets of backplane outputs for optimal COG configurations of the application
图1。PCF85132方框图
图2。PCF85132典型系统配置图
图3。两个采用内部主时钟的PCF85132级联配置图
图3。采用内部主时钟的一个PCF85132和一个PCF85133级联配置图
责任编辑:HanFeng
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