原标题：Lattice LatticeECP3 HDR-60高清视频开发方案

　　lattice 公司的HDR-60高清视频开发板是采用第三代LatticeECP3器件LatticeECP3™-70 FPGA,是低成本评估和演示平台,可以进行评估,测试和调试图像信号处理,和NanoVesta Head Board一起,组成了视频照相机开发套件.采用的传感器是 Aptina公司的A-1000 HDRI 传感器,主要应用在安全监视照乡机和汽车照相机,以太网IP照相机, Teradek H.264压缩模块的评估.本文介绍了LatticeECP3器件主要特性和方框图,以及HDR-60高清视频开发板主要特性,方框图,详细电路图和元件布局图.

　　The LatticeECP3?(EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

　　The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards.

　　The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities.

　　The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS.

　　The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-emphasis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.

　　The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features.

　　The Lattice Diamond?and ispLEVER?design software allows large complex designs to be efficiently implemented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.

　　Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

　　LatticeECP3主要特性:

　　Higher Logic Density for Increased System Inte

　　• 17K to 149K LUTs

　　• 133 to 586 I/Os

　　Embedded SERDES

　　• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes

　　• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

　　• Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO

　　sysDSP™

　　• Fully cascadable slice architecture

　　• 12 to 160 slices for high performance multiply and accumulate • Powerful 54-bit ALU operations

　　• Time Division Multiplexing MAC Sharing

　　• Rounding and truncation

　　• Each slice supports

　　–Half 36x36, two 18x18 or four 9x9 multipliers

　　–Advanced 18x36 MAC and 18x18 Multiply-Multiply-Accumulate (MMAC) operations

　　Flexible Memory Resources

　　• Up to 6.85Mbits sysMEM™ Embedded Block RAM (EBR)

　　• 36K to 303K bits distributed RAM

　　sysCLOCK Analog PLLs and DLLs

　　• Two DLLs and up to ten PLLs per device

　　Pre-Engineered Source Synchronous I/O

　　• DDR registers in I/O cells

　　• Dedicated read/write levelling functionality

　　• Dedicated gearing logic

　　• Source synchronous standards support

　　–ADC/DAC, 7:1 LVDS, XGMII

　　–High Speed ADC/DAC devices

　　• Dedicated DDR/DDR2/DDR3 memory with DQS support

　　• Optional Inter-Symbol Interference (ISI)  correction on outputs 

　　Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

　　• On-chip termination

　　• Optional equalization filter on inputs

　　• LVTTL and LVCMOS 33/25/18/15/12

　　• SSTL 33/25/18/15 I, II

　　• HSTL15 I and HSTL18 I, II

　　• PCI and Differential HSTL, SSTL

　　• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS 

　　Flexible Device Configuration

　　• Dedicated bank for configuration I/Os

　　• SPI boot flash interface

　　• Dual-boot images supported

　　• Slave SPI

　　• TransFR™ I/O for simple field updates

　　• Soft Error Detect embedded macro 

　　System Level Support

　　• IEEE 1149.1 and IEEE 1532 compliant

　　• Reveal Logic Analyzer

　　• ORCAstra FPGA configuration utility

　　• On-chip oscillator for initialization & general use

　　• 1.2V core power supply

　　LatticeECP3™ 系列产品:

　　图1.LatticeECP3-35简化方框图(顶层)

　　HDR-60高清视频开发板

　　The HDR-60 Base Board provides a low-cost evaluation and demonstration platform to evaluate, test and debug image signal processing user designs or IP, including High Dynamic Range (HDR) cores targeted for the LatticeECP3™-70 FPGA. The HDR-60 Base Board and NanoVesta Head Board have been designed to work together as part of the HDR-60 Video Camera Development Kit. Connections are available on the HDR-60 Base Board for the A-1000 HDRI sensor from Aptina, scalable to future sensors from Aptina, and adaptable to sensors from other manufacturers by redesigning the add-on NanoVesta Head Board. The HDR-60 Base Board features a LatticeECP3-70 FPGA in the 484-ball fpBGA package. The LatticeECP3 I/Os are connected to a rich variety of both generic and application-specific interfaces described later in this document.

　　HDR-60高清视频主要特性:

　　Key features of the HDR-60 Base Board include:

　　•SPI serial Flash device included for low-cost, non-volatile configuration storage

　　•DDR2 SDRAM: 16-bit data over a 32M address space

　　•Tri-speed (10/100/1000 Mbit) Ethernet PHY with RJ-45 (includes 12 core magnetics)

　　•Can be re-configured for a BNC Ethernet connection over coaxial cable

　　•Built-in USB 2.0 download to LatticeECP3

　　•Can be configured for a flywire ispDOWNLOAD™ cable connection

　　•HiSPi and parallel video data path connections with selectable VCCIO (1.8V/2.5V/3.3V)

　　•Connectors for Aptina standard Head Board with USB 2.0 interface

　　•Connector for Teradek Capella H.264 codec board

　　•Test point connections to 19 I/O pins for prototyping

　　•Two MEMS and two crystal oscillators

　　•HDMI/DVI output using four channels (one quad) of differential SERDES

　　•5.0V, 3.3V, 2.5V, 1.8V, 1.2V voltages are generated from a single 12V power source

　　•ispVM™ System programming support

　　HDR-60高清视频开发板主要应用:

　　Some common uses for the HDR-60 Base Board include:

　　•Security/surveillance and automotive camera applications

　　•Evaluation of the Helion NanoVesta Head Board and other camera sensors

　　•Applications using Aptina Head Boards

　　•Evaluation of Helion IONOS Imaging Pipeline IP cores

　　•Ethernet IP camera applications

　　•Evaluation of Teradek H.264 compression modules

　　图2.HDR-60高清视频开发板方框图

　　图3.HDR-60高清视频开发板外形图(顶视图)

　　图4.HDR-60基板方框图