原标题：Avnet Xilinx Zynq-7000系列Microzed应用开发方案

　　Xilinx公司的Zynq-7000系列是基于Xilinx全编程的系统级芯片(SoC)架构,集成了富有特性的双核ARM® Cortex™-A9处理系统(PS)和28nm Xilinx 可编逻辑(PL),同时还集成了存储器,外接存储器接口和各种外设连接接口,主要用在汽车辅助驾驶,驾驭信息和娱乐系统,广播摄像机,工业马达控制,工业网络和机器视频,IP和智能相机,LTE无线电和基带,医疗诊断和成像以及视频和夜视设备.本文介绍了Xilinx Zynq-7000系列主要特性和框图,以及Avnet MicroZed Zynq™评估开发板主要特性,框图,电路图,材料清单和PCB元件布局图.

　　The Zynq®-7000 family is based on the Xilinx All Programmable SoC architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.

　　The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 All Programmable SoC family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices.

　　As a result, the Zynq-7000 All Programmable SoCs are able to serve a wide range of applications　including:

　　• Automotive driver assistance, driver information, and infotainment

　　• Broadcast camera

　　• Industrial motor control, industrial networking, and machine vision

　　• IP and Smart camera

　　• LTE radio and baseband

　　• Medical diagnostics and imaging

　　• Multifunction printers

　　• Video and night vision equipment

　　The Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS. It allows for the realization of unique and differentiated system functions. The integration of the PS with the PL allows levels of performance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency, and power budgets.

　　Xilinx offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. The Vivado® Design Suite development environment enables a rapid product development for software, hardware, and systems engineers. Adoption of the ARM-based PS also brings a broad range of third-party tools and IP providers in combination with Xilinx’s existing PL ecosystem.

　　The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating systems used with the Cortex-A9 processor are also available for the Zynq-7000 family.

　　The PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for power management if required. The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.

　　Zynq-7000系列主要特性:

　　Processing System (PS)

　　Dual-core ARM® Cortex™-A9 Based Application Processor Unit (APU)

　　• 2.5 DMIPS/MHz per CPU

　　• CPU frequency: Up to 1 GHz

　　• Coherent multiprocessor support

　　• ARMv7-A architecture

　　• TrustZone® security

　　• Thumb®-2 instruction set

　　• Jazelle® RCT execution Environment Architecture

　　• NEON™ media-processing engine

　　• Single and double precision Vector Floating Point Unit (VFPU)

　　• CoreSight™ and Program Trace Macrocell (PTM)

　　• Timer and Interrupts

　　• Three watchdog timers

　　• One global timer

　　• Two triple-timer counters

　　Caches

　　• 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)

　　• 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)

　　• Byte-parity support

　　On-Chip Memory

　　• On-chip boot ROM

　　• 256 KB on-chip RAM (OCM)

　　• Byte-parity support

　　External Memory Interfaces

　　• Multiprotocol dynamic memory controller

　　• 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories

　　• ECC support in 16-bit mode

　　• 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories

　　• Static memory interfaces

　　• 8-bit SRAM data bus with up to 64 MB support

　　• Parallel NOR flash support

　　• ONFI1.0 NAND flash support (1-bit ECC)

　　• 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash

　　8-Channel DMA Controller

　　• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support

　　I/O Peripherals and Interfaces

　　• Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support

　　• Scatter-gather DMA capability

　　• Recognition of 1588 rev. 2 PTP frames

　　• GMII, RGMII, and SGMII interfaces

　　• Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints

　　• USB 2.0 compliant device IP core

　　• Supports on-the-go, high-speed, full-speed, and low-speed modes

　　• Intel EHCI compliant USB host

　　• 8-bit ULPI external PHY interface

　　• Two full CAN 2.0B compliant CAN bus interfaces

　　• CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant

　　• External PHY interface

　　• Two SD/SDIO 2.0/MMC3.31 compliant controllers

　　• Two full-duplex SPI ports with three peripheral chip selects

　　• Two high-speed UARTs (up to 1 Mb/s)

　　• Two master and slave I2C interfaces

　　• GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic

　　• Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments

　　Interconnect

　　• High-bandwidth connectivity within PS and between PS and PL

　　• ARM AMBA® AXI based

　　• QoS support on critical masters for latency and bandwidth control

　　Programmable Logic (PL)

　　Configurable Logic Blocks (CLB)

　　• Look-up tables (LUT)

　　• Flip-flops

　　• Cascadeable adders

　　36 Kb Block RAM

　　• True Dual-Port

　　• Up to 72 bits wide

　　• Configurable as dual 18 Kb

　　DSP Blocks

　　• 18 x 25 signed multiply

　　• 48-bit adder/accumulator

　　• 25-bit pre-adder

　　Programmable I/O Blocks

　　• Supports LVCMOS, LVDS, and SSTL

　　• 1.2V to 3.3V I/O

　　• Programmable I/O delay and SerDes

　　JTAG Boundary-Scan

　　• IEEE Std 1149.1 Compatible Test Interface

　　PCI Express Block

　　• Supports Root complex and End Point configurations

　　• Supports up to Gen2 speeds

　　• Supports up to 8 lanes

　　Serial Transceivers

　　• Up to 16 receivers and transmitters

　　• Supports up to 12.5 Gb/s data rates

　　Two 12-Bit Analog-to-Digital Converters

　　• On-chip voltage and temperature sensing

　　• Up to 17 external differential input channels

　　• One million samples per second maximum conversion rate

　　Zynq-7000系列主要特性表:

　　图1. Zynq-7000系列方框图

　　MicroZed Zynq™评估开发板

　　图2. MicroZed Zynq™评估开发板外形图

　　The MicroZed is a low cost evaluation board and system on module (SOM) targeted for broad use in many applications. The features provided by the MicroZed consist of:

　　• Xilinx XC7Z010-1CLG400C AP SOC o Primary configuration = QSPI Flash

　　o Auxiliary configuration options  JTAG (through PL via Xilinx PC4 Header)  microSD Card

　　• Memory o 1 GB DDR3 (x32)

　　o 128 Mb QSPI Flash

　　o 4 GB microSD Card

　　• Interfaces o Xilinx PC4 Header for programming  Accesses Programmable Logic (PL) JTAG

　　 Processing System (PS) JTAG pins connected through Digilent Pmod™ compatible interface

　　o 10/100/1000 Ethernet

　　o USB Host 2.0

　　o microSD Card

　　o USB 2.0 Full-Speed USB-UART bridge

　　o One Digilent Pmod compatible interface, connected to PS MIO

　　o Two 100-pin MicroHeaders

　　o Reset Button

　　o 1 User Push Button

　　o 1 User LEDs

　　o DONE LED

　　• On-board Oscillator o 33.333 MHz

　　• Power o High-efficiency regulators for Vccint, Vccpint, Vccbram, Vccaux, Vccpaux, Vccpll, Vcco_0, Vcco_ddr, Vcco_mio

　　o Three potential powering methods  USB Bus Power from USB-UART interface

　　 Optional barrel jack and AC/DC supply

　　 Optional carrier card

　　• Software o Vivado Design Suite  Download from www.xilinx.com/support/download.html

　　 Request a free DVD from www.xilinx.com/onlinestore/dvd_fulfillment_request.htm

　　o Vivado Design Suite: Design Edition license voucher (node-locked, device-locked to the XC7Z010)

　　图3. MicroZed Zynq™评估开发板框图

　　MicroZed Zynq™评估开发板材料清单(BOM):