原标题：Cypress CY8CPLC20可编高压动力线通信开发方案

　　cypress公司的CY8CPLC20是可编高压动力线通信(PLC) PSoC,集成了动力线调制解调器PHY和网络协议堆栈,采用功能强大的哈佛架构处理器M8C,速度高达成24MHz,有两个8x8乘法器和32位累加器,实现频移键控调制,波特率高达2400bps,是动力线通信(PLC)解决方案.本文介绍了CY8CPLC20主要特性,逻辑框图,PSoC核框图,数字和模拟系统框图,以及CY3274可编高压动力线通信(PLC)开发板主要特性,框图,电路图,材料清单和PCB设计图.

　　The CY8CPLC20 is an integrated powerline communication (PLC) chip with the powerline modem PHY and network protocol stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress’s revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.

　　Powerlines are available everywhere in the world and are a widely available communication medium for PLC technology. The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication has been an engineering challenge for years. The Cypress PLC solution enables secure and reliable communications. Cypress PLC features that enable robust communication over powerlines include:

　　■ Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines.

　　■ Powerline optimized network protocol that supports bidirectional communication with acknowledgement-based signaling. In case of data packet loss due to bursty noise on the powerline, the transmitter has the capability to retransmit data.

　　■ The powerline network protocol also supports an 8-bit CRC for error detection and data packet retransmission.

　　■ A Carrier sense multiple access (CSMA) scheme is built into the network protocol that minimizes collisions between packet transmissions on the powerline and supports multiple masters and reliable communication on a bigger network.

　　CY8CPLC20主要特性:

　　■ Powerline communication solution

　　❐ Integrated powerline modem PHY

　　❐ Frequency shift keying modulation

　　❐ Configurable baud rates up to 2400 bps

　　❐ Powerline optimized network protocol

　　❐ Integrates data link, transport, and network layers

　　❐ Supports bidirectional half duplex communication

　　❐ 8-bit CRC error detection to minimize data loss

　　❐ I2C enabled powerline application layer

　　❐ Supports I2C frequencies of 50, 100, and 400 kHz

　　❐ Reference designs for 110 V/240 V AC and 12 V/24 V AC/DC Powerlines

　　❐ Reference designs comply with CENELEC EN 50065-1:2001 and FCC Part 15

　　■ Powerful Harvard-architecture Processor

　　❐ M8C processor speeds to 24 MHz

　　❐ Two 8x8 multiply, 32-bit accumulate

　　■ Programmable system resources (PSoC® Blocks)

　　❐ 12 Rail-to-Rail Analog PSoC Blocks provide:

　　• Up to 14-bit ADCs

　　• Up to 9-bit DACs

　　• Programmable gain amplifiers

　　• Programmable filters and comparators

　　❐ 16 Digital PSoC Blocks provide:

　　• 8 to 32-bit Timers, Counters, and PWMs

　　• CRC and PRS Modules

　　• Up to four full duplex UARTs

　　• Multiple SPI™ masters or slaves

　　• Connectable to all GPIO Pins

　　❐ Complex peripherals by combining blocks

　　■ Flexible on-chip memory

　　❐ 32 KB flash program storage 50,000 erase or write cycles

　　❐ 2 KB SRAM data storage

　　❐ EEPROM emulation in flash

　　■ Programmable pin configurations

　　❐ 25 mA sink, 10 mA source on all GPIOs

　　❐ Pull-up, Pull-down, high Z, strong, or open drain drive Modes on all GPIO

　　❐ Up to 12 analog inputs on all GPIOs

　　❐ Configurable interrupt on all GPIOs

　　■ Additional system resources

　　❐ I2C slave, master, and multi-master to 400 kHz

　　❐ Watchdog and sleep timers

　　❐ User-configurable low-voltage detection

　　❐ Integrated supervisory circuit

　　❐ On-chip precision voltage reference

　　■ Complete development tools

　　❐ Free development software (PSoC Designer™)

　　❐ Full-featured in-circuit emulator (ICE) and programmer

　　❐ Full-speed emulation

　　❐ Complex breakpoint structure

　　❐ 128 KB trace memory

　　❐ Complex events

　　❐ C Compilers, assembler, and linker

　　图1. CY8CPLC20逻辑框图

　　CY8CPLC20 PSoC核

　　The CY8CPLC20 is based on the Cypress PSoC® 1 architecture. The PSoC platform consists of many Programmable System-on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/Os are included in a range of convenient pinouts and packages.

　　The PSoC architecture consists of four main areas: PSoC Core, digital system, analog system, and system resources. Configurable global busing enables all the device resources to be combined into a complete custom system. The CY8CPLC20 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks.

　　The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O).

　　The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a 4 MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to simplify programming of realtime embedded events.

　　Program execution is timed and protected using the included Sleep and Watchdog timers (WDT).Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using Flash. Program Flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection.

　　The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5 percent over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for the digital system use. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. When operating the powerline transceiver (PLT) user module, the ECO must be selected to ensure accurate protocol timing. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

　　PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, enabling great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.

　　图2. PSoC核框图

　　图3.数字系统框图

　　图4.模拟系统框图

　　CY3274可编高压动力线通信(PLC)开发板

　　The CY3274 Programmable High Voltage Powerline Communication Development Kit is a tool to do system design using the ability of the CY8CPLC20 devices to transmit data up to 2400 bps over High Voltage (110V-240V AC) Powerlines. This kit is compliant with FCC(North America) and CENELEC (Europe) standards.

　　图5. CY3274可编高压动力线通信(PLC)开发板外形图

　　CY3274可编高压PLC开发板主要特性:

　　User friendly PLC Control Panel Application available on kit CD

　　CY8CPLC20-OCD – 100-pin TQFP on-chip debug (OCD) device that allows quick design and debug of a PLC application. The CY8CPLC20 100-pin TQFP is available for debug purposed only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.

　　Chip power supply derived from 90V to 264V AC

　　User configurable general purpose LEDs

　　General purpose 8-bit DIP switch

　　On board surge protection and isolation circuit

　　RJ45 connector to use ICE debugger

　　RS232 COM port for communication

　　Header to attach LCD card

　　I2C header for communicating to external device

　　ISSP header for programming the CY8CPLC20

　　CY3274可编高压PLC开发板包括:

　　■ CY3274 quick start guide

　　■ CY3274 PLC HV development board

　　■ AC power cable

　　■ MiniProg1 to program CY8CPLC20

　　■ 25 jumper wires

　　■ LCD module

　　■ USB-I2C bridge

　　■ USB A to mini B cable

　　■ Five CY8CPLC20-28PVXI Device Samples

　　图6.两节点PLC系统框图

　　CY3274可编高压PLC开发板材料清单: