原标题：Lattice MachXO3LF PLD系列入门开发方案

　　lattice公司的MachXO3LF是超低容量的PLD系列,支持最先进的可编桥式和IO扩展,查找表(LUT)从640到6900个,基于LUT的低成本可编逻辑具有嵌入区块RAM(EBR),分布式RAM,锁相环(PLL),并支持用户闪存(UFM),可用在低成本量大的消费类电子和系统应用如无线通信,工业控制系统,计算和存储等.本文介绍了MachXO3LF主要特性,框图,以及MachXO3LF入门板主要功能和特性,框图,电路图和材料清单.

　　MachXO3TM device family is an Ultra-Low Density family that supports the most advanced programmable bridging and IO expansion. It has the breakthrough IO density and the lowest cost per IO. The device IO features have the integrated support for latest industry standard IO. The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 6900 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features allow these devices to be used in low cost, high volume consumer and sys-tem applications. The MachXO3L/LF devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family. The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E are functionally compatible with each other.

　　The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 x 2.5 mm WLCSP to the 17 x 17 mm caBGA. MachXO3L/LF devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters. The MachXO3L/LF devices offer enhanced I/O features such as drive strength control, slew rate control, PCI com-patibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines. The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-anno-tate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

　　MachXO3LF主要特性:

　　•High IO/logic, lowest cost/IO, high IO devices for IO expansion applications

　　•High IO to LUT ratio with up to 335 IO pins

　　•0.8mm pitch: 1K to 6.9K densities with up to 335 IOs in BGA packages

　　•Generic DDR, DDRx2, DDRx4

　　— LVCMOS 3.3/2.5/1.8/1.5/1.2

　　— LVTTL

　　— LVDS, Bus-LVDS, MLVDS, LVPECL

　　— MIPI D-PHY Emulated

　　— Schmitt trigger inputs, up to 0.5 V hysteresis

　　•Programmable pull-up or pull-down mode Solutions

　　•Smallest footprint, lowest power, high data throughput bridging solutions for mobile applica-tions

　　•Optimized footprint, logic density, IO count, IO performance devices for IO management and logic applications Flexible Architecture

　　•Logic Density ranging from 640 to 6.9K LUT4

　　Advanced Packaging

　　• 0.4 mm pitch: 1K to 4K densities in very small footprint WLCSP (2.5 mmx2.5 mm to 3.8 mm x 3.8 mm) with 28 to 63 IOs

　　• 0.5 mm pitch: 640 to 6.9K LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to 281 IOs Pre-Engineered Source Synchronous I/O

　　• DDR registers in I/O cells

　　• Dedicated gearing logic

　　• 7:1 Gearing for Display I/Os

　　High Performance, Flexible I/O Buffer

　　• Programmable sysIOTM buffer supports wide range of interfaces:

　　• Ideal for IO bridging applications

　　• I/Os support hot socketing

　　• On-chip differential termination

　　Flexible On-Chip Clocking

　　• Eight primary clocks

　　• Up to two edge clocks for high-speed I/O inter-faces (top and bottom sides only)

　　• Up to two analog PLLs per device with frac-tional-n frequency synthesis

　　— Wide input frequency range (7 MHz to 400 MHz)

　　— Powers up in microseconds

　　— Supports background programming of non-volatile memory

　　•In-field logic update while IO holds the system state

　　•IEEE 1532 compliant in-system programming

　　•Automotive System 

　　Non-volatile, Multi-time Programmable

　　• Instant-on

　　• Optional dual boot with external SPI memory

　　• Single-chip, secure solution

　　• Programmable through JTAG, SPI or I2C

　　• MachXO3L includes multi-time programmable NVCM

　　• MachXO3LF infinitely reconfigurable Flash 

　　TransFR Reconfiguration 

　　Enhanced System Level Support

　　• On-chip hardened functions: SPI, I2C, timer/ counter

　　• On-chip oscillator with 5.5% accuracy

　　• Unique TraceID for system tracking

　　• Single power supply with extended operating range

　　• IEEE Standard 1149.1 boundary scan

　　Low Cost Migration Path

　　• Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

　　• Pin compatible and equivalent timing

　　MachXO3LF应用:

　　• Consumer Electronics

　　• Compute and Storage

　　• Wireless Communications

　　• Industrial Control Systems

　　

　　图1.MachXO3L/LF框图

　　图2.MachXO3L/LF-4300框图

　　MachXO3LF入门板

　　The MachXO3LF Starter Kit is a basic breakout board to allow simple evaluation and development of MachXO3LF based designs. It has the LCMXO3LF-6900C-5BG256C device on it. A SPI Flash is available on this Starter Kit board for evaluating external boot or dual-boot functional capabilities.

　　This Starter Kit board is a 3 x 3 inch form factor, and features a USB mini-B connector for power and programming, an LED array, and prototype area. It comes with a pre-loaded demonstration, a counter design that highlights use of the embedded MachXO3LF oscillator and programmable I/Os configured for LED drive. A USB cable is also included with the kit, and demos area available for download. By using the free Lattice design tools, you can program the MachXO3LF device to review your own custom design.

　　MachXO3LF入门板主要功能:

　　Evaluate CMOS I/Os

　　LED driving capability

　　Programming via JTAG or I2C

　　SPI flash for external boot or dual-boot operation

　　MachXO3LF入门板主要特性:

　　MachXO3 FPGA – LCMXO3LF-6900C-5BG256C

　　USB Mini-B connector (program/power)

　　Pre-programmed example design (available on latticesemi.com)

　　Eight LEDs

　　4-position DIP switch

　　40-hole Prototyping area

　　Four 2 x 20 expansion header landing for general I/O, JTAG and external power

　　1 x 8 expansion header landing for JTAG

　　1 x 6 expansion header landing for SPI/ I2C

　　SPI Flash for external boot or dual boot

　　3.3 V and 1.2 V supply rails

　　RoHS-compliant

　　Kit Contents

　　MachXO3LF Breakout Board

　　Pre-loaded Demo

　　Mini USB Cable

　　QuickStart Guide

　　图3.MachXO3L入门板外形图(正面)

　　图4.MachXO3L入门板外形图(背面)

　　图5.MachXO3L/LF-6900入门板框图

　　MachXO3L入门板材料清单: