原标题：Altera Arria V高性能28nmSoC FPGA开发方案

　　Altera公司的Arria V是业界最高性能的28nmSoC FPGA系列,其硬件处理器系统(HPS)包含双核ARM® Cortex™-A9处理器(工作频率高达1.05GHz),外设和存储器接口以及28nm FPGA架构,具有最低的总功耗,可降低系统成本和空间.处理器和FPGA互连大于125Gbps总带宽,最低功耗的收发器速率高达10.3125 Gbps,主要用在无线基础设备,有线10G/40G线卡和GPON,军用设备,测试测量设备,医疗图像设备和多功能打印机以及广播设备.本文介绍了Arria V SoC系列FPGA主要特性,架构图,以及Altera®Arria V SoC开发板主要特性,框图,电路图,材料清单和PCB元件布局图.

　　Altera’s Arria® V SoC is the industry’s highest performance 28 nm SoC FPGA with the lowest total power for midrange applications such as remote radio units, 10G/40G line cards, medical imaging, and broadcast studio equipment. The combination of a hard processor system (HPS) consisting of a dual-core ARM® Cortex™-A9 processor, peripherals, and memory interfaces with flexible 28 nm FPGA fabric lets you reduce system power, cost, and board space.

　　Industry’s Highest Performance 28nm SoC FPGA

　　Up to 1.05 GHz dual-core ARM® Cortex™-A9 MPCore processor

　　4 hardened 32-bit memory controllers with up to 533 MHz memory bus speed and optional ECC

　　Processor to FPGA interconnect with >125 Gbps peak total bandwidth

　　Lowest System Power for Midrange Applications

　　Integration of multiple components into a single chip

　　Lowest power transceivers with speeds up to 10.3125 Gbps

　　Based on low power TSMC 28LP process

　　Multiple Benefits to System Cost

　　Integration of multiple components into a single chip

　　PCB cost and trace savings from integration of processor, FPGA and DSP into a single device

　　No power-off sequencing requirements

　　Arria V SoC系列应用:

　　The Arria V SoCs have been designed to meet the performance, power, and cost requirements for applications such as:

　　Wireless infrastructure equipment including remote radio units and mobile backhaul

　　Wireline 10G/40G line cards, bridges and aggregation, GPON

　　Broadcast studio and distribution equipment including professional A/V and video conferencing

　　Military guidance, control, and intelligence equipment

　　Test and measurement equipment

　　Medical imaging equipment

　　Multifunction Printers

　　The Arria® V SoC integrates a dual-core ARM® Cortex™-A9 hard processor system (HPS), embedded peripherals, multiport memory controllers, serial transceivers, PCI Express® (PCIe®) ports and Arria V FPGA fabric into a single, high performance device.

　　Arria V SoC系列主要特性:

　　图1.Arria V SoC系列架构图

　　Altera®Arria V SoC开发板

　　The Altera® Arria® V system on a chip (SoC) Development Kit is a complete design

　　environment that includes both the hardware and software you need to develop

　　Arria V SoC designs.

　　Altera®Arria V SoC开发板主要特性:

　　■ One Arria V SoC (5ASTFD5K3F40I3) in a 896-pin FBGA package

　　■ FPGA configuration circuitry

　　■ Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N)

　　■ MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the System

　　Controller

　　■ Flash fast passive parallel (FPP) configuration

　　■ MAX II CPLD (EPM570GF100) as part of the on-board USB-BlasterTM II for use

　　with the Quartus® II Programmer

　　■ Clocking circuitry

　　■ Si570, Si571, and Si5338 programmable oscillators

　　■ 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators

　　■ SMA input (LVCMOS)

　　■ Memory

　　■ One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC)

　　support

　　■ Two 1,024-MB FPGA DDR3 SDRAM

　　■ One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash

　　■ One 512-Mb CFI synchronous flash

　　■ One 256-Mb NOR flash (EPCQ device)

　　■ One 32-Kilobit (Kb) I2C serial electrically erasable PROM (EEPROM)

　　■ One Micro SD flash memory card

　　■ Communication Ports

　　■ One PCI Express x4 Gen1 socket

　　■ Two FPGA mezzanine card (FMC) ports

　　■ One USB 2.0 on-the-go (OTG) port

　　■ One Gigabit Ethernet port

　　■ Two 10/100 Ethernet ports

　　■ Two SFP+ ports

　　■ Two RS-232 UART (through the mini-USB port)

　　■ One real-time clock

　　■ General user input/output

　　■ LEDs and displays

　　■ Eight user LEDs

　　■ One configuration load LED

　　■ One configuration done LED

　　■ One error LED

　　■ Three configuration select LEDs

　　■ Four on-board USB-Blaster II status LEDs

　　■ Two FMC interface LEDs

　　■ Two UART data transmit and receive LEDs

　　■ One power on LED

　　■ One two-line character LCD display

　　■ Push buttons

　　■ One CPU reset push button

　　■ One MAX V reset push button

　　■ One program select push button

　　■ One program configuration push button

　　■ Eight general user push buttons

　　■ DIP switches

　　■ One JTAG chain control DIP switch

　　■ One board settings DIP switch

　　■ One FPGA configuration mode DIP switch

　　■ One general user DIP switch

　　■ Power supply

　　■ 14–20-V (laptop) DC input

　　■ Mechanical

　　■ 7.175" × 9" rectangular form factor

　　图2.Altera®Arria V SoC开发板外形图

　　图3.Altera®Arria V SoC开发板框图

　　Altera®Arria V SoC开发板主要元件表:

　　图4.Altera®Arria V SoC开发板电路图(1)